The present invention relates to the field of electronic devices having memory arrays, and is more specifically directed to redundancy schemes in such devices.
A redundant column is a column of memory cells that can replace a defective or malfunctioning memory column of a memory device. A fatal defect in one memory cell makes the cell inoperable. If the cell is not replaced the entire memory device can malfunction. Replacing a column containing a defect in one of its memory cells with a redundant column can make a memory device that would otherwise have been unusable usable, therefore greatly improving the yield of memory devices.
As the trend to increase the density of components per unit area of semiconductor devices continues, the size of the defect that can cause failure also shrinks. Additionally, as the size and total number of components in a memory device continues to increase so does the cost of each memory device, and therefore the cost of each non-usable memory device. Redundant columns are often used in memory devices to prevent an isolated defect from destroying the entire device.
Memory cells are usually arranged in rows and columns, and grouped into blocks composed of columns arranged into input/output groups. A memory cell's address is the intersection of its row and column.
The defects in the memory cells are discovered in initial testing and the redundant columns replace the columns containing defective cells. When a defect is found in a memory cell the address of a redundant column is conventionally mapped to the address of the column containing the defective cell. Therefore, when a read or write access is addressed to a bad column, the redundancy control logic will divert the read or write operation, so that the data is read or written into the appropriate location in the redundant column, which had been selected to replace the defective column. Thus, the outside system never sees the remapping performed by the redundancy logic.
The redundancy logic should operate fast enough so that the normal access times are preserved. If access time of a redundant column is significantly slower than the access time of a non-redundant, or primary column, the access time of the redundant column becomes the access time of the system. This imposes a speed penalty on the system for using redundant columns.
A goal in the semiconductor industry is to increase the speed of the circuit. Both the access time of the primary circuit and the amount of time that is considered to be a significant difference between the access time of the redundant and primary columns have decreased. A problem presented in the prior art is that redundancy logic has not been able to accommodate this increase in speed. The access time of the redundant column can now impose a speed penalty for accessing the redundant columns.
Additionally, redundant columns and redundant select circuitry to allow for the selection of the redundant columns increases the complexity of the memory device. This increases both the manufacturing time and the cost of the memory device. It is therefore necessary to balance the probable number of columns that have memory cells with defects with the cost of each additional redundant column to determine the number of redundant columns to add to the memory device. Reducing the complexity of the redundancy architecture without adversely affecting the flexibility and speed of the redundant column select has long been goal in memory design.
Further background on memories and on column redundancy can be found in: Prince, Betty, SEMICONDUCTOR MEMORIES, A HANDBOOK OF DESIGN, MANUFACTURE, AND APPLICATION, 2.sup.nd ed., John Wiley & Sons, 1991; Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. Solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43; and Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51; ISSCC proceedings from 1975 to the present, all incorporated herein by reference.